1. Field of the Invention
The invention relates to a method of fabricating flash memory devices and, more particularly, to flash memory devices and a method of fabricating the same, where inter-cell interference can be reduced without lowering the program speed.
2. Discussion of Related Art
As the level of integration of semiconductor devices increases, isolation films are formed using the Self-Aligned Shallow Trench Isolation (SA-STI) method in the manufacturing process.
The structure of a flash memory cell in which the isolation films is formed by the SA-STI method is described below.
FIG. 1 is a cross-sectional view illustrating a method of fabricating a flash memory cell and the structure thereof in the related art.
Referring to FIG. 1, tunnel oxide films 102, and a first polysilicon layer 103 for forming a floating gate are sequentially formed on a semiconductor substrate 101. The first polysilicon layer 103 and the tunnel oxide films 102 are patterned by the SA-STI method, forming isolation films 104 in the isolation regions.
If the isolation films 104 are formed by the SA-STI method as described above, the tunnel oxide films 102 and the first polysilicon layer 103 remain on the active regions between the projections of the isolation films 104 while the top surfaces of the isolation films 104 project higher than the semiconductor substrate 101.
A second polysilicon layer 105 for forming a floating gate is then formed on the entire surface. The second polysilicon layer 105 on the isolation films 104 is then partially removed by an etch process so that it is patterned in a direction vertical to the line. At this time, since some of the second polysilicon layer 105 on the isolation films 104 is removed, the edges of the second polysilicon layer 105 overlap with the isolation films 104 (indicated by “A” in FIG. 1). A floating gate 106 having first and second polysilicon layers 103, 105 is thereby completed.
Thereafter, an interlayer dielectric film 107 of an Oxide-Nitride-Oxide (ONO) structure and a polysilicon layer 108 for a control gate are formed on the entire surface. A tungsten silicide layer (not shown) for lowering surface resistance is formed on the polysilicon layer 108 for the control gate. The tungsten silicide layer, the polysilicon layer 108 for the control gate, the interlayer dielectric film 107 and the floating gate 106 are patterned by a photolithography process, forming a gate. A subsequent process is then performed to complete the fabrication of the flash memory device.
The flash memory cell is a device that stores and reads information through the migration of the threshold voltage in a state where electrons are injected into the floating gate and a state where electrons are not injected into the floating gate. The program speed is proportional to an overlap area between the control gate and the floating gate, i.e., the coupling ratio.
Meanwhile, inter-cell interference in which the threshold voltage is influenced depending on the state of peripheral cells becomes great as the area of the floating gate becomes wide.
In the inter-cell interference phenomenon, the threshold voltage of the program cell is varied depending on whether peripheral cells have been programmed. As a result, as the cell distribution is widened that much, the characteristics and uniformity of the device are degraded.
If the area of the second polysilicon layer 105 is wide as in the related art, the cell distribution is increased due to inter-cell interference. If the width of the second polysilicon layer 105 is reduced in order to reduce the cell distribution, problems arise because the coupling ratio is reduced and the program speed is lowered.